The present invention relates to a liquid crystal display device; and, more particularly, the invention relates to a technique that is effective when applied to a driving circuit of the liquid crystal display device, in a system for transferring a digital signal between driving circuits (drain drivers).
A liquid crystal display module of the STN (super Twisted Nematic) system or the TFT (Thin film Transistor) system, having a large-sized liquid crystal display panel with a pixel number of e.g., 800×480×3, or more in a panel capable of producing a color display, is widely used as a display device in a notebook type of personal computer, etc. These liquid crystal display devices have a liquid crystal display panel and a driving circuit for operating the liquid crystal display panel.
For example, JP-A-6-13724/1994, discloses a method (hereinafter called a digital signal sequential transfer method) in which a digital signal (e.g., display data or a clock signal) is inputted to only the head driving circuit of cascade-connected driving circuits, and then the digital signal is sequentially transferred to the other driving circuits through the interior of the driving circuits in a liquid crystal display device. In the liquid crystal display device described in this publication (JP-A-6-13724/1994), a semiconductor integrated circuit device (IC) constituting the driving circuit is directly mounted on a glass substrate of the liquid crystal display panel.
FIG. 9 is a block diagram showing the basic construction of a liquid crystal display panel employed in a conventional liquid crystal display device using the digital signal sequential transfer method mentioned above. In the liquid crystal display panel shown in this figure, a timing controller (or a display control device) 110, a plurality of drain drivers 130 and a plurality of gate drivers 140 are respectively mounted on peripheral portions along two sides of a transparent insulating substrate (glass substrate) constituting a TFT substrate of the liquid crystal display panel 100.
A digital signal (display data, a clock signal, etc.), that is sent from the timing controller 110, and a gray scale reference voltage, that is supplied from a power source circuit, are inputted to the head drain driver 130, and these signals are propagated in respective internal signal line within each drain driver 130 and on respective transmission line paths (a wiring layer on the glass substrate) between the respective drain drivers 130, and are, in this way, inputted to each drain driver 130. The source voltage of each drain driver 130 is supplied from a power source circuit 120 to each drain driver 130 through a flexible printed wiring board (hereinafter simply called an FPC board) 150.
Similarly, the digital signal (clock signal, etc.) sent from the timing controller 110 is inputted to the head gate driver 140, and this signal is propagated in an internal signal line within each gate driver 140 and a transmission line path between the respective gate drivers 140, and is, in this way, inputted to each gate driver 140. However, on the gate driver side, the source voltage of the gate driver 140, that is supplied from the power source circuit 120, is also supplied to the head gate driver 140, and this voltage is supplied to each gate driver 140 through an internal power source line within each gate driver 140 and a transmission line path between the respective gate drivers 140.